High Speed Synchronization for a Statically Scheduled Superscalar Processor

T. Arita and M. Sowa

International Journal of High Speed Computing, Vol. 3, No. 1, pp. 77-87, World Scientific, 1991
Superscalar processors can execute multiple scalar instructions in parallel. Conventional statically scheduled superscalar processors have drawbacks when it comes to dynamic variations in instruction latency. In this paper a very simple synchronization method is described for a statically scheduled superscalar processor consisting of multiple functional units each processing its own instruction stream. This superscalar processor has not only a conventional program counter which is indispensable for the von Neumann execution model but also token counters which express the differences of instructions executed. The simulation results indicate that the superscalar processor with the proposed synchronization shows 33-42% speed up compared with a static VLIW processor and 4-13% speed up compared with a dynamic VLIW processor on the condition that there are dynamic variations in instruction latency.